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integrated silicon solution, inc. www.issi.com 1 rev. d 5/28/2013 copyright ? 2013 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex - pected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is42s16400j is45s16400j features ? clock frequency: 200, 166, 143, 133 mhz ? fully synchronous; all signals referenced to a positive clock edge ? internal bank for hiding row access/precharge ? single 3.3v power supply ? lvttl interface ? programmable burst length C (1, 2, 4, 8, full page) ? programmable burst sequence: sequential/interleave ? self refresh modes ? auto refresh (cbr) ? 4096 refresh cycles every 64 ms (com, ind, a1 grade) or 16ms (a2 grade) ? random column address every clock cycle ? programmable cas latency (2, 3 clocks) ? burst read/write and burst read/single write operations capability ? burst termination by burst stop and precharge command options ? package: 54-pin tsop ii 54-ball tf-bga (8mm x 8mm) 60-ball tf-bga (10.1mm x 6.4mm) ? operating temperature range commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) automotive grade a1 (-40 o c to +85 o c) automotive grade a2 (-40 o c to +105 o c) overview issi 's 64mb synchronous dram is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. the synchronous drams achieve high-speed data transfer using pipeline architecture. all inputs and outputs signals refer to the rising edge of the clock input. 1 meg bits x 16 bits x 4 banks (64-mbit) synchronous dynamic ram may 2013 key timing parameters parameter -5 -6 -7 unit clk cycle time cas latency = 3 5 6 7 ns cas latency = 2 7.5 7.5 7.5 ns clk frequency cas latency = 3 200 166 143 mhz cas latency = 2 133 133 133 mhz access time from clock cas latency = 3 4.8 5.4 5.4 ns cas latency = 2 5.4 5.4 5.4 ns parameter 4m x 16 confguration 1m x 16 x 4 banks refresh count com./ind. a1 a2 4k/64ms 4k/64ms 4k/16ms row addresses a0-a11 column addresses a0-a7 bank address pins ba0, ba1 auto precharge pins a10/ap address table
2 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j general description the 64mb sdram is a high speed cmos, dynamic random-access memory designed to operate in 3.3v memory systems containing 67,108,864 bits. internally confgured as a quad-bank dram with a synchronous interface. each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. the 64mb sdram includes an auto refresh mode, and a power-saving, power-down mode. all signals are registered on the positive edge of the clock signal, clk. all inputs and outputs are lvttl compatible. the 64mb sdram has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. a self-timed row precharge initiated at the end of the burst sequence is available with the auto precharge function enabled. precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. sdram read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. the registration of an active command begins accesses, followed by a read or write command. the active command in conjunction with address bits registered are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a11 select the row). the read or write commands in conjunction with address bits registered are used to select the starting column location for the burst access. programmable read or write burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. clk cke cs ras cas we a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a11 command decoder & clock genera to r mode register refresh contr oller refresh counter self refresh contro ller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder da ta in buffer da ta out buffer dqm dq 0-15 v dd /v ddq gnd/gndq 12 12 8 12 12 8 16 16 16 16 256k (x 16) 4096 4096 4096 ro w decoder 4096 memor y cell arra y ba nk 0 sense amp i/o ga te bank contr ol logic ro w address buffer functional block diagram
integrated silicon solution, inc. www.issi.com 3 rev. d 5/28/2013 is42s16400j is45s16400j pin configuration package code: b 54 ball tf-bga (top view) (8 mm x 8 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j dq15 dq13 dq11 dq9 nc clk a11 a7 a5 gndq vddq gndq vddq gnd cke a9 a6 a4 vddq gndq vddq gndq vdd cas ba0 a0 a3 dq0 dq2 dq4 dq6 dqml ras ba1 a1 a2 gnd dq14 dq12 dq10 dq8 dqmh nc a8 gnd vdd dq1 dq3 dq5 dq7 we cs a10 vdd pin descriptions a0-a11 row address input a0-a7 column address input ba0, ba1 bank select addresses dq0 to dq15 data i/o clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command we write enable ldqm, udqm x16 input/output mask v dd power gnd ground v ddq power supply for i/o pin gndq ground for i/o pin nc no connection
4 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j pin configuration package code: b2 60 ball tf-bga (top view) (10.1 mm x 6.4 mm body, 0.65 mm ball pitch) 1 2 3 4 5 6 7 a b c d e f g h j k l m n p r gnd dq14 dq13 dq12 dq10 dq9 dq8 nc nc nc cke a11 a8 a6 gnd dq15 gndq vddq dq11 gndq vddq nc nc udqm clk nc a9 a7 a5 a4 dq0 vddq gndq dq4 vddq gndq nc vdd ldqm ras nc ba1 a0 a2 a3 vdd dq1 dq2 dq3 dq5 dq6 dq7 nc we cas cs ba0 a10 a1 vdd pin descriptions a 0-a11 row address i nput a0-a7 column address input ba0, ba1 bank select addresses dq0 to dq15 data i/o clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command we write enable ldqm, udqm x16 input/output mask v dd power gnd ground v ddq power supply for i/o pin gnd q ground for i/o pin nc no connection
integrated silicon solution, inc. www.issi.com 5 rev. d 5/28/2013 is42s16400j is45s16400j pin configurations 54 pin tsop - type ii pin descriptions a0-a11 row address input a0-a7 column address input ba0, ba1 bank select address dq0 to dq15 data i/o clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command v dd dq0 v dd q dq1 dq2 gndq dq3 dq4 v dd q dq5 dq6 gndq dq7 v dd ldqm we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 gnd dq15 gndq dq14 dq13 v dd q dq12 dq11 gndq dq10 dq9 v dd q dq8 gnd nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 gnd we write enable ldqm x16 lower byte, input/output mask udqm x16 upper byte, input/output mask power gnd ground v power supply for i/o pin gnd ground for i/o pin nc no connection
6 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j pin functions sym bol tsop pin no. type function a0-a11 23 to 26 input pin address inputs: a0-a11 are sampled during the active 29 to 34 command (row-address a0-a11) and read/write command (a0-a7 22, 35 with a10 defning auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to deter - mine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. ba0, ba1 20, 21 input pin bank select address: ba0 and ba1 defnes which bank the active, read, write or precharge command is being applied. cas 17 input pin cas , in conjunction with the ras and we , forms the device command. see the "command truth table" for details on device commands. cke 37 input pin the cke input determines whether the clk input is enabled. the next rising edge of the clk signal will be valid when is cke high and invalid when low. when cke is low, the device will be in either power-down mode, clock suspend mode, or self refresh mode. cke is an asynchronous i nput. clk 38 input pin clk is the master clock input for this device. except for cke, all inputs to this device are acquired in synchronization with the rising edge of this pin. cs 19 input pin the cs input determines whether command input is enabled within the device. command input is enabled when cs is low, and disabled with cs is high. the device remains in the previous state when cs is high. dq0 to 2, 4, 5, 7, 8, 10, dq pin dq0 to dq15 are i/o pins. i/o through these pins can be controlled in byte units dq15 11,13, 42, 44, 45, using the ldqm and udqm pins. 47, 48, 50, 51, 53 ldqm, 15, 39 input pin ldqm and udqm control the lower and upper bytes of the i/o buffers. in read udqm mode, ldqm and udqm control the output buffer. when ldqm or udqm is low, the corresponding buffer byte is enabled, and when high, disabled. the outputs go to the high impedance state when ldqm/udqm is high. this function cor - responds to oe in conventional drams. in write mode, ldqm and udqm control the input buffer. when ldqm or udqm is low, the corresponding buffer byte is en - abled, and data can be written to the device. when ldqm or udqm is high, input data is masked and cannot be written to the device. ras 18 input pin ras , in conjunction with cas and we , forms the device command. see the "com - mand truth table" item for details on device commands. we 16 input pin we , in conjunction with ras and cas , forms the device command. see the "com - mand truth table" item for details on device commands. v ddq 3, 9, 43, 49 power supply pin v ddq is the output buffer power supply. v dd 1, 14, 27 power supply pin v dd is the device internal power supply. g nd q 6, 12, 46, 52 power supply pin g nd q is the output buffer ground. g nd 28, 41, 54 power supply pin g nd is the device internal ground.
integrated silicon solution, inc. www.issi.com 7 rev. d 5/28/2013 is42s16400j is45s16400j read the read command selects the bank from ba0, ba1 inputs and starts a burst read access to an active row. inputs a0-a7 provides the starting column location. when a10 is high, this command functions as an auto precharge command. when the auto precharge is selected, the row being accessed will be precharged at the end of the read burst. the row will remain open for subsequent accesses when auto precharge is not selected. dqs read data is subject to the logic level on the dqm inputs two clocks earlier. when a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later. dqs will provide valid data when the dqm signal was registered low. write a burst write access to an active row is initiated with the write command. ba0, ba1 inputs selects the bank, and the starting column location is provided by inputs a0-a7. whether or not auto-precharge is used is determined by a10. the row being accessed will be precharged at the end of the write burst, if auto precharge is selected. if auto precharge is not selected, the row will remain open for subsequent accesses. a memory array is written with corresponding input data on dqs and dqm input logic level appearing at the same time. data will be written to memory when dqm signal is low. when dqm is high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. ba0, ba1 can be used to select which bank is precharged or they are treated as dont care. a10 determines whether one or all banks are precharged. after executing this command, the next command for the selected bank(s) is executed after passage of the period t rp , which is the period required for bank precharging. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge the auto precharge function ensures that the precharge is initiated at the earliest valid stage within a burst. this function allows for individual-bank precharge without requiring an explicit command. a10 can be used to enable the auto precharge function in conjunc - tion with a specifc read or write command. for each individual read or write command, auto precharge is either enabled or disabled. auto precharge does not apply except in full-page burst mode. upon completion of the read or write burst, a precharge of the bank/row that is addressed is automatically performed. auto refresh command this command executes the auto refresh operation. the row address and bank to be refreshed are automatically generated during this operation. the stipulated period (t rc ) is required for a single refresh operation, and no other com - mands can be executed during this period. this command is executed at least 4096 times every t ref . during an auto refresh command, address bits are dont care. this command corresponds to cbr auto-refresh. self refresh during the self refresh operation, the row address to be refreshed, the bank, and the refresh interval are gen - erated automatically internally. self refresh can be used to retain data in the sdram without external clocking, even if the rest of the system is powered down. the self refresh operation is started by dropping the cke pin from high to low. during the self refresh operation all other inputs to the sdram become dont care. the device must remain in self refresh mode for a minimum period equal to t ras or may remain in self refresh mode for an indefnite period beyond that. the self-refresh operation continues as long as the cke pin remains low and there is no need for external control of any other pins. the next command cannot be executed until the device internal recovery period (t rc ) has elapsed. once cke goes high, the nop command must be issued (minimum of two clocks) to provide time for the completion of any internal refresh in progress. after the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses. burst terminate the burst terminate command forcibly terminates the burst read and write operations by truncating either fxed-length or full-page bursts and the most recently registered read or write command prior to the burst terminate. command inhibit command inhibit prevents new commands from being executed. operations in progress are not affected, apart from whether the clk signal is enabled no operation when cs is low, the nop command prevents unwanted commands from being registered during idle or wait states.
8 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j load mode register during the load mode register command the mode register is loaded from a0-a11. this command can only be issued when all banks are idle. active command when the active command is activated, ba0, ba1 inputs selects a bank to be accessed, and the address inputs on a0-a11 selects the row. until a precharge command is issued to the bank, the row remains open for accesses.
integrated silicon solution, inc. www.issi.com 9 rev. d 5/28/2013 is42s16400j is45s16400j truth table C commands and dqm operation (1) function cs ras cas we dqm addr dqs command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) (3) l l h h x bank/row x read (select bank/column, start read burst) (4) l h l h l/h (8) bank/col x write (select bank/column, start write burst) (4) l h l l l/h (8) bank/col valid burst terminate l h h l x x active precharge (deactivate row in bank or banks) (5) l l h l x code x auto refresh or self refresh (6,7) l l l h x x x (enter self refresh mode) load mode register (2) l l l l x op-code x write enable/output enable (8) l active write inhibit/output high-z (8) h high-z notes: 1. cke is high for all commands except self refresh. 2. a0-a11 defne the op-code written to the mode register. 3. a0-a11 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-a7 (x16) provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables auto precharge; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are dont care. 6. auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay).
10 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j truth table C current state bank n, command to bank n (1-6) current state command (action) cs ras cas we any command inhibit (nop/continue previous operation) h x x x no operation (nop/continue previous operation) l h h h idle active (select and activate row) l l h h auto refresh (7) l l l h load mode register (7) l l l l precharge (11) l l h l row active read (select column and start read burst) (10) l h l h write (select column and start write burst) (10) l h l l precharge (deactivate row in bank or banks) (8) l l h l read read (select column and start new read burst) (10) l h l h (auto write (select column and start write burst) (10) l h l l precharge precharge (truncate read burst, start precharge) (8) l l h l disabled) burst terminate (9) l h h l write read (select column and start read burst) (10) l h l h (auto write (select column and start new write burst) (10) l h l l precharge precharge (truncate write burst, start precharge) (8) l l h l disabled) burst terminate (9) l h h l note: 1. this table applies when cke n-1 was high and cke n is high (see truth table - cke) and after t xsr has been met (if the previous state was self refresh ). 2. this table is bank-specifc, except where noted; i.e., the current state is for a specifc bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. truth table C cke (1-4) current state commandn actionn cken-1 cken power-down x maintain power-down l l self refresh x maintain self refresh l l clock suspend x maintain clock suspend l l power-down (5) command inhibit or nop exit power-down l h self refresh (6) command inhibit or nop exit self refresh l h clock suspend (7) x exit clock suspend l h all banks idle command inhibit or nop power-down entry h l all banks idle auto refresh self refresh entry h l reading or writing valid clock suspend entry h l see truth table C current state bank n, command to bank n h h notes: 1. cken is the logic state of cke at clock edge n ; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and actonn is a result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that t cks is met) . 6. exiting self refresh at clock edge n will put the device in all banks idle state once t xsr is met. command inhibit or nop commands should be issued on clock edges occurring during the t xsr period. a minimum of two nop commands must be sent during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n+1 .
integrated silicon solution, inc. www.issi.com 11 rev. d 5/28/2013 is42s16400j is45s16400j 3. current state defnitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi - nated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi - nated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable com - mands to the other bank are determined by its current state and current state bank n truth tables. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specifc; requires that all banks are idle. 8. may or may not be bank-specifc; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specifc; burst terminate affects the most recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
12 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j truth table C current state bank n, command to bank m (1-6) current state command (action) cs ras cas we any command inhibit (nop/continue previous operation) h x x x no operation (nop/continue previous operation) l h h h idle any command otherwise allowed to bank m x x x x row active (select and activate row) l l h h activating, read (select column and start read burst) (7) l h l h active, or write (select column and start write burst) (7) l h l l precharging precharge l l h l read active (select and activate row) l l h h (auto read (select column and start new read burst) (7,10) l h l h precharge write (select column and start write burst) (7,11) l h l l disabled) precharge (9) l l h l write active (select and activate row) l l h h (auto read (select column and start read burst) (7,12) l h l h precharge write (select column and start new write burst) (7,13) l h l l disabled) precharge (9) l l h l read active (select and activate row) l l h h (with auto read (select column and start new read burst) (7,8,14) l h l h precharge) write (select column and start write burst) (7,8,15) l h l l precharge (9) l l h l write active (select and activate row) l l h h (with auto read (select column and start read burst) (7,8,16) l h l h precharge) write (select column and start new write burst) (7,8,17) l h l l precharge (9) l l h l note: 1. this table applies when cke n-1 was high and cke n is high (truth table - cke) and after t xsr has been met (if the previ - ous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable) . excep - tions are covered in the notes below. 3. current state defnitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi - nated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi - nated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled.
integrated silicon solution, inc. www.issi.com 13 rev. d 5/28/2013 is42s16400j is45s16400j 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been inter - rupted by bank ms burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later (consecutive read bursts). 11. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will inter - rupt the read on bank n when registered (read to write). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (write to read), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 13. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will inter - rupt the write on bank n when registered (write to write). the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered (fig cap 1). 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (fig cap 2). 16. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in regis - tered one clock prior to the read to bank m (fig cap 3). 17. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (fig cap 4).
14 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j absolute maximum ratings (1) symbol parameters rating unit v dd max maximum supply voltage C1.0 to +4.6 v v dd q max maximum supply voltage for output buffer C1.0 to +4.6 v v in input voltage C1.0 to v ddq + 0.5 v v out output voltage C1.0 to v ddq + 0.5 v p d max allowable power dissipation 1 w i cs o utput shorted current 50 ma t opr o perating temperature com. 0 to +70 c ind. -40 to +85 c a1 -40 to +85 c a2 -40 to +105 c t stg storage temperature C65 to +150 c dc recommended operating conditions (2) ( at t a = 0 to +70c for commercial grade. t a = -40 to +85c for industrial and a1 grade. t a = -40 to +105c for a2 grade) symbol parameter min. typ. max. unit v dd , v dd q supply voltage 3.0 3.3 3.6 v v ih input high voltage (3) 2.0 v dd + 0.3 v v il input low voltage (4) -0.3 +0.8 v capacitance characteristics (1,2) (at t a = 0 to +25c, v dd = v ddq = 3.3 0.3v, f = 1 mhz) symbol parameter typ. max. unit c in input capacitance: address and control 3.8 pf c clk input capacitance: (clk) 3.5 pf ci/o data input/output capacitance: i/o0-i/o15 6.5 pf notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all voltages are referenced to gnd. 3. v ih (max) = v ddq + 1.2v with a pulse width < 3ns. 4. v il (min) = gnd - 1.2v with a pulse width < 3ns. package substrate theta-ja (airfow = 0m/s) theta-ja (airfow = 1m/s) theta-ja (airfow = 2m/s) theta-jc units oor6 odu 77.4 16.1 c/w 7623 51.7 49.0 47.7 11.9 c/w 50.5 44.6 41.7 11.3 c/w 42.3 41 7.5 c/w thermal resistance
integrated silicon solution, inc. www.issi.com 15 rev. d 5/28/2013 is42s16400j is45s16400j dc electrical characteristics 1 (recommended operation conditions unless otherwise noted.) symbol parameter test condition -5 -6 -7 unit i dd 1 (1) operating current one bank active, cl = 3, bl = 1, 90 80 70 ma t clk = t clk (min), t rc = t rc (min) i dd 2 p precharge standby current cke v il ( max ), t ck = 15ns 2 2 2 ma (in power-down mode) cs v dd - 0.2v i dd 2 ps precharge standby current cke v il ( max ), clk v il ( max ) 2 2 2 ma with clock stop cs v dd - 0.2v (in power-down mode) i dd 2 n (2) precharge standby current cs v dd - 0.2v, cke v ih ( min ) 20 20 20 ma (in non power-down mode) t ck = 15ns i dd 2 ns precharge standby current cs v dd - 0.2v, cke v ih ( min ) 10 10 10 ma with clock stop (in non power-down mode) all inputs stable i dd 3 p (2) active standby current cke v il ( max ), cs v dd - 0.2v 6 6 6 ma (in power-down mode) t ck = 15ns i dd 3 ps active standby current cke v il ( max ), clk v il ( max ), 6 6 6 ma with clock stop cs v dd - 0.2v (in power-down mode) i dd 3 n (2) active standby current cs v dd - 0.2v, cke v ih ( min ) 25 25 25 ma (in non power-down mode) t ck = 15ns i dd 3 ns active standby current cs v dd - 0.2v, cke v ih ( min ) 20 20 20 ma with clock stop all inputs stable (in non power-down mode) i dd 4 operating current all banks active, bl = 4, cl = 3, 110 100 90 ma t ck = t ck (min) i dd 5 auto-refresh current t rc = t rc (min), t clk = t clk (min) 110 100 90 ma i dd 6 self-refresh current cke 0.2v 2 2 2 ma notes: 1. i dd ( max ) is specifed at the output open condition. 2. input signals are changed one time during 30ns. dc electrical characteristics 2 (recommended operation conditions unless otherwise noted.) symbol parameter test condition min max unit i il input leakage current 0v vin v dd , with pins other than -5 5 a the tested pin at 0v i ol output leakage current output is disabled, 0v vout v dd , -5 5 a v oh output high voltage level i oh = -2ma 2.4 v v ol output low voltage level i ol = 2ma 0.4 v
16 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j ac electrical characteristics (1,2,3) -5 -6 -7 symbol parameter min. max. min. max. min. max. units t ck 3 clock cycle time cas latency = 3 5 6 7 ns t ck 2 cas latency = 2 7.5 7.5 7.5 ns t ac 3 access time from clk (4,6) cas latency = 3 4.8 5.4 5.4 ns t ac 2 cas latency = 2 5.4 5.4 5.4 ns t ch clk high level width 2 2 2.5 ns t cl clk low level width 2 2 2.5 ns t oh 3 output data hold time (6) cas latency = 3 2.5 2.5 2.7 ns t oh 2 cas latency = 2 2.5 2.5 2.7 ns t lz output low impedance time 0 0 0 ns t hz 3 output high impedance time (5) cas latency = 3 4.8 5.4 5.4 ns t hz 2 cas latency = 2 5.4 5.4 5.4 ns t ds input data setup time 1.5 1.5 1.5 ns t dh input data hold time 0.8 0.8 0.8 ns t as address setup time 1.5 1.5 1.5 ns t ah address hold time 0.8 0.8 0.8 ns t cks cke setup time 1.5 1.5 1.5 ns t ckh cke hold time 0.8 0.8 0.8 ns t cka cke to clk recovery delay time 1clk+3 1clk+3 1clk+3 ns t cms command setup time ( cs , ras , cas , we , dqm) 1.5 1.5 1.5 ns t cmh command hold time ( cs , ras , cas , we , dqm) 0.8 0.8 0.8 ns t rc command period (ref to ref / act to act) 55 60 63 ns t ras command period (act to pre) 40 100,000 42 100,000 42 100,000 ns t rp command period (pre to act) 15 15 15 ns t rcd active command to read / write command delay time 15 15 15 ns t rrd command period (act [0] to act[1]) 10 12 14 ns t dpl or input data to precharge cas latency = 3 2clk 2clk 2clk ns t wr command delay time cas latency = 2 2clk 2clk 2clk ns t dal input data to active / refresh cas latency = 3 2clk+t rp 2clk+t rp 2clk+t rp ns command delay time (during auto-precharge) cas latency = 2 2clk+t rp 2clk+t rp 2clk+t rp ns t t transition time 0.3 1.2 0.3 1.2 0.3 1.2 ns t xsr exit self-refresh to active time 60 66 70 ns t ref refresh cycle time (4096) t a 70 o c com., ind., a1, a2 64 64 64 ms t a 85 o c ind., a1, a2 64 64 ms t a > 85 o c a2 16 ms notes: 1. when power is frst applied, memory operation should be started 200 s after v dd and v ddq reach their stipulated voltages. also note that the power-on sequence must be executed before starting memory operation. 2. m easured with t t = 1 ns. 3. the reference level is 1.4 v when measuring input signal timing. rise and fall times are measured between v ih (min.) and v il ( max.). 4. access time is measured at 1.4v with the load shown in the fgure below. 5. the time t hz ( max.) is defned as the time required for the output voltage to transition by 200 mv from v oh (min.) or v ol (max.) when the output is in the high impedance state. 6. if clock rising time is longer than 1ns, t t / 2 - 0.5ns should be added to the parameter.
integrated silicon solution, inc. www.issi.com 17 rev. d 5/28/2013 is42s16400j is45s16400j ac test conditions (input/output reference level: 1.4v) i/o 50 +1.4v 50 pf input load output load 3.0v 1.4v 0v clk input output t ch t cmh t ac t oh t cms t ck t cl 3.0v 1.4v 1.4v 1.4v 0v operating frequency / latency relationships symbol parameter -5 -6 -7 units t ck clock cycle time cl=3 5 6 7 ns cl=2 7.5 7.5 7.5 ns freq. operating frequency cl=3 200 166 143 mhz cl=2 133 133 133 mhz t ccd read/write command to read/write command 1 1 1 cycle t cked cke to clock disable or power-down entry mode 1 1 1 cycle t ped cke to clock enable or power-down exit setup mode 1 1 1 cycle t dqd dqm to input data delay 0 0 0 cycle t dqm dqm to data mask during writes 0 0 0 cycle t dqz dqm to data high-impedance during reads 2 2 2 cycle t dwd write command to input data delay 0 0 0 cycle t dal data-in to active command cl=3 5 5 5 cycle cl=2 4 4 4 cycle t dpl data-in to precharge command 2 2 2 cycle t bdl last data-in to burst stop command 1 1 1 cycle t cdl last data-in to new read/write command 1 1 1 cycle t rdl last data-in to precharge command 2 2 2 cycle t mrd load mode register command 2 2 2 cycle to active or refresh command t roh data-out to high-impedance from cl=3 3 3 3 cycle precharge command cl=2 2 2 2 cycle
18 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j functional description the 64mb sdrams (1 meg x 16 x 4 banks) are quad-bank drams which operate at 3.3v and include a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac - tive command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-a11 select the row) . the address bits (a0-a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initial - ized. the following sections provide detailed information covering device initialization, register defnition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefned manner. the 64mb sdram is initialized after the power is applied to v dd and v ddq (simultaneously), and the clock is stable with dqm high and cke high. a 100s delay is required prior to issuing any command other than a command inhibit or a nop . the command inhibit or nop may be applied during the 100s period and continue should at least through the end of the period. with at least one command inhibit or nop command having been applied, a precharge command should be applied once the 100s delay has been satisfed. all banks must be precharged. this will leave all banks in an idle state, after which at least two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is then ready for mode register programming. the mode register should be loaded prior to applying any operational command because it will power up in an unknown state. after the load mode register command, at least one nop command must be asserted prior to any command.
integrated silicon solution, inc. www.issi.com 19 rev. d 5/28/2013 is42s16400j is45s16400j register definition mode register the mode register is used to defne the specifc mode of operation of the sdram. this defnition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in mode register definition. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifes the type of burst (sequential or interleaved) , m4- m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifes the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specifed time before initiating the subsequent operation. violating either of these requirements will result in unspecifed operation. mode register definition latency mode m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 1. to ensure compatibility with future devices, should program m11, m10 = "0, 0" write burst mode m9 mode 0 programmed burst length 1 single location access operating mode m8 m7 m6-m0 mode 0 0 defined standard operation ? ? ? all other states reserved burst type m3 type 0 sequential 1 interleaved burst length m2 m1 m0 m3=0 m3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 f ull page reserved reserved address bus mode register (mx) a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 (1)
20 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a7 cn, cn + 1, cn + 2 not supported page cn + 3, cn + 4... (y) (location 0-y) cn - 1, cn burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in mode register definition. the burst length deter - mines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean - ing that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 (x16) when the burst length is set to two; by a2-a7 (x16) when the burst length is set to four; and by a3-a7 (x16) when the burst length is set to eight. the remaining (least signifcant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition table.
integrated silicon solution, inc. www.issi.com 21 rev. d 5/28/2013 is42s16400j is45s16400j don't care undefined clk command dq read nop nop nop cas latency - 3 t ac t oh d out t0 t1 t2 t3 t4 t lz clk command dq read nop nop cas latency - 2 t ac t oh d out t0 t1 t2 t3 t lz cas latency cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the frst piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in cas latency diagrams. the allowable operating frequency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. cas latency allowable operating frequency (mhz) speed cas latency = 2 cas latency = 3 -5 133 200 -6 133 166 -7 133 143 operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used be - cause unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses.
22 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j clk cke high - z row address bank address cs ras cas we a0-a11 ba0, ba1 activating specifc row within specifc bank don't care clk command ac tive nop nop t rcd t0 t1 t2 t3 t4 read or write operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated (see activating specifc row within specifc bank ). after opening a row (issuing an active command) , a read or write command may be issued to that row, subject to the t rcd specifcation. minimum t rcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specifcation of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is refected in the following example, which cov - ers any case where 2 < [t rcd (min)/t ck ] 3. (the same procedure is used to convert other specifcation limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successive active commands to the same bank is defned by t rc . a subsequent active command to another bank can be issued while the frst bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defned by t rrd . example: meeting t rcd (min) when 2 < [t rcd (min)/t ck ] 3
integrated silicon solution, inc. www.issi.com 23 rev. d 5/28/2013 is42s16400j is45s16400j clk cke high-z column address auto precharge no precharge cs ras cas we a0-a7 a10 ba0, ba1 bank address a8, a9, a11 read command reads read bursts are initiated with a read command, as shown in the read command diagram. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the fol - lowing illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. the cas latency diagram shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a sub - sequent read command, and data from a fxed-length read burst may be immediately followed by data from a read command. in either case, a continuous fow of data can be maintained. the frst data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in consecutive read bursts for cas latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architec - ture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in random read accesses, or each subsequent read may be performed to a different bank. data from any read burst may be truncated with a sub - sequent write command, and data from a fxed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge im - mediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a pos - sibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures rw1 and rw2. the dqm signal must be as - serted (high) at least three clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure rw2, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. a fxed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated) , and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in the read to precharge
24 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care undefined clk command dq read nop nop nop cas latency - 3 t ac t oh d out t0 t1 t2 t3 t4 t lz clk command dq read nop nop cas latency - 2 t ac t oh d out t0 t1 t2 t3 t lz cas latency diagram for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fxed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fxed-length burst with auto precharge. the disadvantage of the pre - charge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fxed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fxed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in the read burst termination diagram for each possible cas latency; data element n + 3 is the last desired data element of a longer burst.
integrated silicon solution, inc. www.issi.com 25 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop read nop nop d out n d out n+1 d out n+2 d out n+3 d out b bank, col n bank, col b cas latency - 2 x = 1 cycle don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop read nop nop nop d out n d out n+1 d out n+2 d out n+3 d out b bank, col n bank, col b cas latency - 3 x = 2 cycles consecutive read bursts
26 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command address dq t0 t1 t2 t3 t4 t5 read read read read nop nop d out n d out b d out m d out x bank, col n bank, col b cas latency - 2 bank, col m bank, col x don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read read read read nop nop nop d out n d out b d out m d out x bank, col n bank, col b cas latency - 3 bank, col m bank, col x random read accesses
integrated silicon solution, inc. www.issi.com 27 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 read nop nop nop nop write bank, col n bank, col b d out n d in b t ds t hz cas latency - 3 rw1 - read to write rw2 - read to write don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop write bank, col n d in b t ds t hz bank, col b cas latency - 2 d out n d out n+1 d out n+2
28 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop nop ac t ive d out n d out n+1 d out n+2 d out n+3 bank a, col n bank a, ro w bank (a or all) cas latency - 2 x = 1 cycle t rp precharge don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop nop ac tive d out n d out n+1 d out n+2 d out n+3 bank, col n bank, col b cas latency - 3 x = 2 cycles t rp bank a, ro w precharge read to precharge
integrated silicon solution, inc. www.issi.com 29 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop d out n d out n+1 d out n+2 d out n+3 bank a, col n cas latency - 2 x = 1 cycle b urst termina te don't care clk command address dq t0 t1 t2 t3 t4 t5 t6 t7 read nop nop nop nop nop nop d out n d out n+1 d out n+2 d out n+3 bank, col n cas latency - 3 x = 2 cycles burs t termina te read burst termination
30 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j clk cke high - z column address auto precharge bank address cs ras cas we a0-a7 a10 ba0, ba1 no precharge a8, a9, a11 write command the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the frst valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive posi - tive clock edge. upon completion of a fxed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see write burst). a full-page burst will con - tinue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data for any write burst may be truncated with a subse - quent write command, and data for a fxed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. an example is shown in write to write diagram. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2n rule as - sociated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in random write cycles, or each subsequent write may be performed to a different bank. data for any write burst may be truncated with a subse - quent read command, and data for a fxed-length write burst may be immediately followed by a subsequent read command. once the read command is registered, the data inputs will be ignored, and writes will not be ex - ecuted. an example is shown in write to read. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fxed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti - vated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in the write to pre - charge diagram. data n +1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fxed-length burst being executed to comple - tion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fxed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fxed-length or full-page bursts. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncat - ing a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in write burst termination, where data n is the last desired data element of a longer burst. writes write bursts are initiated with a write command, as shown in write command diagram.
integrated silicon solution, inc. www.issi.com 31 rev. d 5/28/2013 is42s16400j is45s16400j clk command address dq t0 t1 t2 t3 write nop nop nop d in n d in n+1 bank, col n don't care clk command address dq t0 t1 t2 write nop write d in n d in n+1 d in b bank, col n bank, col b don't care write burst write to write clk command address dq t0 t1 t2 t3 write write write write d in n d in b d in m d in x bank, col n bank, col b bank, col m bank, col x random write cycles
32 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command address dq t0 t1 t2 t3 t4 t5 write nop read nop nop nop d in n d in n+1 d out b d out b+1 bank, col n bank, col b cas latency - 2 write to read wp1 - write to precharge don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 write nop nop ac tive nop nop bank a, col n bank a, ro w bank (a or all) t wr t rp precharge d in n d in n+1 cas latency - 2
integrated silicon solution, inc. www.issi.com 33 rev. d 5/28/2013 is42s16400j is45s16400j clk command address dq t0 t1 t2 write d in n (d ata ) bank, col n don't care (address) burs t termina te next command write burst termination don't care clk dqm command address dq t0 t1 t2 t3 t4 t5 t6 write nop nop nop ac tive nop bank a, col n bank a, ro w bank (a or all) t wr t rp precharge d in n d in n+1 cas latency - 3 wp2 - write to precharge
34 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j clk cke high - z all banks bank select bank address cs ras cas we a0-a9, a11 a10 ba0, ba1 don't care clk cke command nop nop a ctive t cks t cks all banks idle enter po wer-do wn mode exit po wer-do wn mode t rcd t ras t rc input b uff ers gated off precharge command power-down power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cs ). see fgure below. precharge the precharge command (see fgure) is used to deac - tivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specifed time (t p ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank.
integrated silicon solution, inc. www.issi.com 35 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk cke command address dq t0 t1 t2 t3 t4 t5 nop write nop nop bank a, col n d in n d in n+1 d in n+2 internal clock don't care clk cke command address dq t0 t1 t2 t3 t4 t5 t6 read nop nop nop nop nop bank a, col n d out n d out n+1 d out n+2 d out n+3 internal clock clock suspend clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see following examples.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. clock suspend during write burst clock suspend during read burst
36 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d out a d out a+1 d out b d out b+1 bank n, col a bank m, col b cas latency - 3 (bank n) cas latency - 3 (bank m) t rp - bank n t rp - bank m read - ap bank n read - ap bank m pa ge activ e read with burst of 4 interr upt burst, precharge idle pa ge activ e read with burst of 4 precharge inter nal states don't care clk command bank n bank m address dqm dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d out a d in b d in b+1 d in b+2 d in b+3 bank n, col a bank m, col b cas latency - 3 (bank n) t rp - bank n t rp - bank m write - ap bank n write - ap bank m read with burst of 4 interr upt burst, precharge idle pa ge activ e write with burst of 4 wr ite-bac k inter nal states p age activ e burst read/single write the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. issi sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defned below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. f ig cap 1 - read with auto precharge interrupted by a read f ig cap 2 - read with auto precharge interrupted by a write
integrated silicon solution, inc. www.issi.com 37 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop d in a d in a+1 d out b d out b+1 bank n, col a bank m, col b cas latency - 3 (bank m) t rp - bank n t rp - bank m write - ap bank n read - ap bank m pa ge activ e write with burst of 4 interr upt burst, wr ite-bac k precharge pa ge activ e read with burst of 4 precharge inter nal states t wr - bank n don't care clk command bank n bank m address dq t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop bank n, col a bank m, col b t rp - bank n t rp - bank m write - ap bank n write - ap bank m pa ge activ e write with burst of 4 interr upt burst, wr ite-bac k precharge pa ge activ e write with burst of 4 wr ite-bac k inter nal states t wr - bank n d in a d in a+1 d in a+2 d in b d in b+1 d in b+2 d in b+3 write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t is met, where t begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t is met, where t begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m. f ig cap 3 - write with auto precharge interrupted by a read f ig cap 4 - write with auto precharge interrupted by a write
38 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j initialize and load mode register (1) don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t ch t cl t ck t cms t cmh t cms t cmh t cms t cmh t cks t ckh t0 t1 tn+1 t o+1 tp+1 tp+2 tp+3 t mrd t rc t rc t rp ro w ro w bank t as t ah t as t ah code code all banks single bank all banks au to refresh au to refresh load mode register t = 100s min. po wer-up: v cc and clk stab le precharge all banks au to refresh program mode register nop precharge nop nop nop a ctive t (2, 3, 4) au to refresh at least 2 a uto-refresh commands notes: 1. if cs is high at clock high time, all commands applied are nop. 2. the mode register may be loaded prior to the auto-refresh cycles if desired. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high-z after the command is issued.
integrated silicon solution, inc. www.issi.com 39 rev. d 5/28/2013 is42s16400j is45s16400j power-down mode cycle cas latency = 2, 3 don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t as t ah bank t ch t cl t ck t cms t cmh t cks t ckh precharge nop nop nop ac tive all banks single bank ro w ro w bank t cks t cks precharge all activ e banks all banks idle tw o cloc k cycles input b uff ers gated off while in po wer-do wn mode all banks idle , enter po wer-do wn mode exit p ow er-do wn mode t0 t1 t2 tn+1 tn+2 high-z
40 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j clock suspend mode notes: 1. cas latency = 3, burst length = 2 2. a 8 , a 9 , and a 11 = "don't care" don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ch t cl t ck t cms t cmh t cks t ckh column m (2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 read nop nop nop nop nop write nop t cks t ckh bank bank column n (2) t ac t ac t oh t hz d out m d out m+1 t lz undefined d out e+1 t ds t dh d out e
integrated silicon solution, inc. www.issi.com 41 rev. d 5/28/2013 is42s16400j is45s16400j auto-refresh cycle cas latency = 2, 3 t rp t rc t rc don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t as t ah t ch t cl t ck t cms t cmh t cks t ckh t0 t1 t2 tn+1 to +1 all banks single bank bank (s) ro w ro w bank high-z precharge nop nop nop a ctive au to refresh au to refresh
42 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j self-refresh cycle note: 1. self-refresh mode is not supported for a2 grade with t a > 85 o c. clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t as t ah bank t cl t ch t ck t cms t cmh t cks t ckh all banks single bank t cks precharge all activ e banks clk stab le pr ior to e xiting self refresh mode enter self refresh mode exit self refresh mode (restar t refresh time base) t0 t1 t2 tn+1 to +1 to +2 high-z au to refresh au to refresh precharge nop nop nop t cks t ras t rp t xsr don't care
integrated silicon solution, inc. www.issi.com 43 rev. d 5/28/2013 is42s16400j is45s16400j read without auto precharge don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop precharge nop ac tive t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd cas latency t ac t ac t ac t ac t oh t hz t oh d out m t oh d out m+1 t oh d out m+2 d out m+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 disable au to precharge ro w ro w bank t lz t ras t rc t rp all banks single bank bank notes: 1. cas latency = 2, burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
44 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j read with auto precharge don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop nop nop ac tive t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t ac t ac t ac t oh t hz t oh d out m t oh d out m+1 t oh d out m+2 d out m+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp enable au to precharge ro w ro w bank t lz notes: 1. cas latency = 2, burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
integrated silicon solution, inc. www.issi.com 45 rev. d 5/28/2013 is42s16400j is45s16400j single read without auto precharge don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop precharge nop a ctive nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t hz t oh d out m t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp disable au to precharge ro w ro w bank t lz all banks single bank bank notes: 1. cas latency = 2, burst length = 1 2. a 8 , a 9 , and a 11 = "don't care"
46 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j single read with auto precharge don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop nop nop read nop nop a ctive nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd t ras t rc cas latency t ac t hz t oh d out m t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp enable au to precharge ro w ro w bank notes: 1. cas latency = 2, burst length = 1 2. a 8 , a 9 , and a 11 = "don't care"
integrated silicon solution, inc. www.issi.com 47 rev. d 5/28/2013 is42s16400j is45s16400j alternating bank read accesses bank 0 bank 3 bank 3 bank 0 don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd - bank 0 cas latency - bank 0 t rcd - bank 0 t ras - bank 0 t rc - bank 0 t ch t cl t ck t cms t cmh t cks t ckh a ctive nop read nop ac tive nop read nop a ctive ro w ro w bank 0 ro w ro w t rrd t rcd - bank 3 t rp - bank 0 column m (2) ro w column b (2) ro w enable au to precharge enable au to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t ac t oh t oh t oh t oh t oh d out m d out m+ 1 d out m+ 2 d out m+ 3 d out b t ac t ac t ac t ac t ac t lz cas latency - bank 3 notes: 1. cas latency = 2, burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
48 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j read - full-page burst don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop read nop nop nop nop nop burst term nop nop t as t ah t as t ah t as t ah ro w ro w bank column m (2) t ch t cl t ck t cms t cmh t cks t ckh bank t rcd cas latency t ac t ac t ac t ac t ac t hz t lz t ac t oh t oh t oh t oh t oh t oh d out m d out m+ 1 d out m+ 2 d out m- 1 d out m d out m+ 1 each ro w (x4) has 1,024 locations full page completion full-page b urst not self-ter minating. use burst termina te command. t0 t1 t2 t3 t4 t5 t6 tn+1 tn+2 tn+3 tn+4 notes: 1. cas latency = 2, burst length = full page 2. a 8 , a 9 , and a 11 = "don't care"
integrated silicon solution, inc. www.issi.com 49 rev. d 5/28/2013 is42s16400j is45s16400j read - dqm operation don't care undefined clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh ac tive nop read nop nop nop nop nop nop t as t ah t as t ah t as t ah enable au to precharge disable au to precharge ro w ro w bank t rcd cas latency d out m d out m+ 2 d out m+ 3 column m (2) bank t ch t cl t ck t cms t cmh t cks t ckh t oh t oh t oh t ac t ac t ac t hz t hz t lz t lz t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 1. cas latency = 2, burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
50 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j write - without auto precharge don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop nop nop precharge nop ac tive t wr (3) t rp column m (2) ro w disable au to precharge ro w ro w ro w bank t ds t dh t ds t dh t ds t dh t ds t dh d in m d in m+ 1 d in m+ 2 d in m+ 3 bank bank bank all banks single bank t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 1. burst length = 4 2. a 8 , a 9 , and a 11 = "don't care" 3. t ras must not be violated
integrated silicon solution, inc. www.issi.com 51 rev. d 5/28/2013 is42s16400j is45s16400j write - with auto precharge don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop nop nop nop nop nop ac tive t wr t rp column m (2) ro w bank bank enable au to precharge ro w ro w ro w bank t ds t dh t ds t dh t ds t dh t ds t dh d in m d in m+ 1 d in m+ 2 d in m+ 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 notes: 1. burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
52 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j single write - without auto precharge don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop write nop (4) nop (4) precharge nop ac tive nop t wr (3) t rp disable au to precharge ro w ro w ro w bank d in m column m (2) ro w bank bank bank all banks single bank t0 t1 t2 t3 t4 t5 t6 t7 t8 notes: 1. burst length = 1 2. a 8 , a 9 , and a 11 = "don't care" 3. t ras must not be violated
integrated silicon solution, inc. www.issi.com 53 rev. d 5/28/2013 is42s16400j is45s16400j single write - with auto precharge don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t rcd t ras t rc t ch t cl t ck t cms t cmh t cks t ckh a ctive nop (3) nop (3) nop (3) write nop nop nop ac tive nop t wr t rp column m (2) ro w bank bank enable au to precharge ro w ro w ro w bank d in m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 notes: 1. burst length = 1 2. a 8 , a 9 , and a 11 = "don't care"
54 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j alternating bank write access bank 0 bank 1 bank 1 bank 0 don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh t rcd - bank 0 t rcd - bank 0 t wr - bank 1 t ras - bank 0 t rc - bank 0 t ch t cl t ck t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t cms t cmh t cks t ckh a ctive nop write nop a ctive nop write nop nop a ctive d in m d in m+ 1 d in m+ 2 d in m+ 3 d in b d in b+ 1 d in b+ 2 d in b+ 3 ro w ro w bank 0 ro w ro w t rrd t rcd - bank 1 t wr - bank 0 t rp - bank 0 column m (2) ro w column b (2) ro w enable au to precharge enable au to precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 notes: 1. burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
integrated silicon solution, inc. www.issi.com 55 rev. d 5/28/2013 is42s16400j is45s16400j don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh a ctive nop write nop nop nop nop burst term nop t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh ro w ro w bank t rcd d in m d in m+ 1 d in m+ 2 d in m+ 3 d in m- 1 column m (2) t ch t cl t ck t ds t dh t ds t dh t ds t dh t cms t cmh t cks t ckh bank full page completed t0 t1 t2 t3 t4 t5 tn+1 tn+2 write - full page burst notes: 1. burst length = full page 2. a 8 , a 9 , and a 11 = "don't care"
56 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j don't care clk cke command dqm/ dqml, dqmh a0-a9, a11 a10 ba0, ba1 dq t cms t cmh ac tive nop write nop nop nop nop nop t as t ah t as t ah t as t ah t ds t dh t ds t dh t ds t dh enable au to precharge disable au to precharge ro w ro w bank t rcd d in m d in m+ 2 d in m+ 3 column m (2) bank t ch t cl t ck t cms t cmh t cks t ckh t0 t1 t2 t3 t4 t5 t6 t7 write - dqm operation notes: 1. burst length = 4 2. a 8 , a 9 , and a 11 = "don't care"
integrated silicon solution, inc. www.issi.com 57 rev. d 5/28/2013 is42s16400j is45s16400j ordering information commercial range: 0 c to 70 c frequency speed (ns) order part no. package 200 mhz 5 is42s16400j-5tl 54-pin tsopii, alloy42 leadframe plated with matte sn is42s16400j-5bl 54-ball bga, snagcu balls 166 mhz 6 IS42S16400J-6TL 54-pin tsopii, alloy42 leadframe plated with matte sn is42s16400j-6bl 54-ball bga, snagcu balls 143 mhz 7 is42s16400j-7tl 54-pin tsopii, alloy42 leadframe plated with matte sn is42s16400j-7bl 54-ball bga, snagcu balls industrial range: -40 c to 85 c frequency speed (ns) order part no. package 200 mhz 5 is42s16400j-5bli 54-ball bga, snagcu balls 166 mhz 6 IS42S16400J-6TLi 54-pin tsopii, alloy42 leadframe plated with matte sn is42s16400j-6bli 54-ball bga, snagcu balls 143 mhz 7 is42s16400j-7tli 54-pin tsopii, alloy42 leadframe plated with matte sn is42s16400j-7bli 54-ball bga, snagcu balls is42s16400j-7b2li 60-ball bga, snagcu balls automotive range (a1): -40 c to 85 c frequency speed (ns) order part no. package 200 mhz 5 is45s16400j-5tla1 54-pin tsopii, alloy42 leadframe plated with matte sn is45s16400j-5ctla1 54-pin tsopii, cu leadframe plated with matte sn is45s16400j-5bla1 54-ball bga, snagcu balls 166 mhz 6 is45s16400j-6tla1 54-pin tsopii, alloy42 leadframe plated with matte sn is45s16400j-6ctla1 54-pin tsopii, cu leadframe plated with matte sn is45s16400j-6bla1 54-ball bga, snagcu balls 143 mhz 7 is45s16400j-7tla1 54-pin tsopii, alloy42 leadframe plated with matte sn is45s16400j-7ctla1 54-pin tsopii, cu leadframe plated with matte sn is45s16400j-7bla1 54-ball bga, snagcu balls automotive range (a2): -40 c to 105 c frequency speed (ns) order part no. package 143 mhz 7 is45s16400j-7tla2 54-pin tsopii, alloy42 leadframe plated with matte sn is45s16400j-7ctla2 54-pin tsopii, cu leadframe plated with matte sn is45s16400j-7bla2 54-ball bga, snagcu balls notes: 1. contact issi for leaded and copper leadframe parts support. 2. part numbers with "l" or "n" are leadfree, and rohs compliant.
58 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j
integrated silicon solution, inc. www.issi.com 59 rev. d 5/28/2013 is42s16400j is45s16400j package outline 10/17/2007
60 integrated silicon solution, inc. www.issi.com rev. d 5/28/2013 is42s16400j is45s16400j

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